MOS (metal oxide silicon) devices are being made smaller and smaller according to a need for high-integration of semiconductor devices. For example, channel width is being reduced to sub-micron levels to increase the operating speed and current drive capability of semiconductor devices.
In a CMOS (complementary metal oxide silicon) semiconductor device a MOS device is generally used together with an NMOS transistor in which a P channel MOS transistor and an N-channel MOS transistor are formed in one semiconductor device so as to perform a complementary operation. Accordingly dual gates have been used. Dual gates generally reinforce the semiconductor function of a channel surface layer and therefore produce a desired symmetrical low-voltage operation. In fabricating a CMOS semiconductor device employing a dual gate, boron or BF2 is generally used to dope the polysilicon gate electrode of a PMOS transistor.
Unfortunately, when boron has been used as the impurity, it has been likely that the boron would penetrate a thin gate insulation layer and diffuse into the channel during a subsequent annealing process, etc. This diffusion of boron into the channel decreases the mobility of charges in the channel. Also, impurity depletion in the gate electrode may occur and may further form a P-type impurity layer near the channel connecting the source and drain. This results in an increased operating voltage, which of course hinders high integration. Furthermore, the operating voltage becomes unpredictable since boron does not always diffuse into the channel, making high integration even more difficult. This diffusion problem may become even more serious when BF2 is used as the impurity to make a shallower and narrower source/drain because boron is even more likely to diffuse when fluorine reactions are present.
Describing the aforementioned impurity depletion in the gate electrode in more detail, the solubility of solid boron in polysilicon is generally low. Therefore, even if the penetration of boron is high, the boron may not be distributed evenly within the polysilicon gate layer and a depleted region could form in the gate electrode adjacent to the gate insulation layer. If a depletion region forms adjacent to the gate insulation layer, a voltage applied to the gate electrode will not have a sufficient influence upon the channel. Therefore, the formation of a depletion region is another cause of an increase in the threshold voltage.
A conventional method of fabricating a transistor of a DRAM (dynamic random access memory) semiconductor device will be described according to the prior art, referring to FIGS. 1a to 1v. 
Referring to FIG. 1a, a pad oxide layer 12, a molding polysilicon layer 14 and a hard mask layer 16 are formed on a semiconductor substrate 10 that is doped with a P-type impurity.
Referring to FIG. 1b, a photoresist is deposited on the hard mask layer 16, and the photoresist is patterned through a photolithography process to expose a portion of the hard mask layer 16. The hard mask layer 16 is selectively etched through the patterning of photoresist to expose the molding polysilicon layer 14, thus defining an active region A.
In FIG. 1c, the molding polysilicon layer 14, the pad oxide layer 12 and the semiconductor substrate 10 are partially removed to form a trench T.
Referring to FIG. 1d, the surface of the exposed molding polysilicon layer 14 and semiconductor substrate 10 is selectively oxidized through a thermal oxide process by using the hard mask layer 16 as an oxide stop mask, and a device isolation film 18 is formed. The substrate is flattened so as to partially expose the semiconductor substrate.
In FIG. 1e, a photoresist 20 is deposited on the semiconductor substrate 10, and the photoresist 20 is partially etched to expose a cell region X of the semiconductor substrate 10. A P-type impurity of a low dose such as boron or BF2 is selectively ion-implanted into the active region of the cell region X by using the photoresist 20 as an ion implantation mask, to form a channel impurity region 22 of low density, and then the photoresist 20 is removed.
With reference to FIG. 1f, the photoresist 20 is deposited on the semiconductor substrate 10, and the photoresist 20 is partially removed to expose an NMOS transistor region N of the circuit region Y of the semiconductor substrate 10. A P-type impurity of a low dose such as boron or BF2 is ion-implanted into the NMOS transistor region of the circuit region Y by using the photoresist 20 as an ion implantation mask to form the channel impurity region 22 of low density, and then the photoresist 20 is removed.
With reference to FIG. 1g, the photoresist 20 is deposited on the semiconductor substrate 10, and the photoresist 20 is partially removed to expose a PMOS transistor region P of the circuit region Y of the semiconductor substrate 10. An N-type impurity of a low dose such as phosphorous or As is ion-implanted into the PMOS transistor region of the circuit region Y by using the photoresist 20 as an ion implantation mask to form the channel impurity region 22 of low density. Then the photoresist 20 is removed.
In FIG. 1h, a gate insulation layer 24 is formed with a predetermined thickness on the semiconductor substrate 10 through the use of a silicon oxide layer subject to a thermal oxide process, and a polysilicon gate electrode 26 is formed on the gate insulation layer 24.
In FIG. 1i, the photoresist 20 is deposited on the substrate, and the photoresist 20 is partially removed to expose the gate electrode 26 of the NMOS transistor region N of the cell region Y and the circuit region X by using the photolithography process. An N-type impurity is implanted into the gate electrode 26 of the NMOS transistor region N of the cell region Y and the circuit region X, and then the photoresist 20 is removed.
In FIG. 1j, the photoresist 20 is deposited on the substrate, and the photoresist 20 is partially removed to expose the gate electrode 26 of the PMOS transistor region P of the circuit region Y by using the photolithography process. A P-type impurity is implanted into the gate electrode 26 of the PMOS transistor region P, and then the photoresist 20 is removed.
In FIG. 1k, a conductive metal layer 28 is formed on the gate electrode 26, and a gate upper insulation layer 30 is formed on the conductive metal layer 28 by using a silicon nitride layer, etc.
Referring to FIG. 11, the photoresist (not shown) is deposited on the gate upper insulation layer 30, and the photoresist is partially removed through a photolithography process. Next, the gate upper insulation layer 30, the conductive metal layer 28 and the gate electrode 26 are partially removed to expose a portion of the gate insulation layer 24 by using the photoresist as an etch mask, and then the photoresist is removed.
In FIG. 1m, the photoresist 20 is deposited on an entire face of the substrate, and the photoresist 20 is partially removed to expose the cell region X. A N-type impurity of a low dose such as phosphorous or As is ion-implanted into an exposed source/drain region (S/D) by using the photoresist 20 and the upper insulation layer 30 as an ion implantation mask to form a first impurity region 32 of low density, and then the photoresist 20 is removed.
In FIG. 1n, the photoresist 20 is deposited on an entire face of the substrate, and the photoresist 20 is partially removed to expose the NMOS transistor region N of the circuit region Y. An N-type impurity of a low dose such as phosphorous or As is ion-implanted into the S/D by using the photoresist 20 and the upper insulation layer 30 of the circuit region Y as an ion implantation mask to form the first impurity region 32 of low density, and then the photoresist 20 is removed.
In FIG. 1o, the photoresist 20 is deposited on an entire face of the substrate, and the photoresist 20 is partially removed to expose the PMOS transistor region P of the circuit region Y. A P-type impurity of a low dose such as boron or BF2 is ion-implanted into the S/D by using the photoresist 20 and the upper insulation layer 30 as an ion implantation mask to form the first impurity region 32 of low density, and then the photoresist 20 is removed. Subsequently, in order to reduce a lattice defect of the semiconductor substrate 10 generated by the ion implantation, an annealing process of high temperature, e.g. about 800° C., is performed.
With reference to FIG. 1p, a silicon nitride layer is formed on an entire face of the substrate, and a spacer 34 is formed on a sidewall of the gate electrode 26.
In FIG. 1q, the photoresist 20 is deposited on an entire face of the substrate, and the photoresist 20 is partially removed to expose the NMOS transistor region N of the circuit region Y. An N-type impurity of a high dose is ion-implanted by using the photoresist 20, upper insulating layer 30, and the spacer 34 as an ion implantation mask to form a second impurity region 36 of high density, and then the photoresist 20 is removed.
In FIG. 1r, the photoresist 20 is deposited on an entire face of the substrate, and the photoresist 20 is partially removed to expose the PMOS transistor region P of the circuit region Y. A P-type impurity of a high dose is ion-implanted by using the photoresist 20, the upper insulating layer 30, and the spacer 34 as an ion implantation mask to form the second impurity region 36 of high density, and then the photoresist 20 is removed.
In FIG. 1s, an interlayer insulation layer 38 is formed with silicon oxide on the semiconductor substrate 10 and then the interlayer insulation layer 38 is flattened to expose the gate upper insulation layer 30 and the spacer 34 through a chemical mechanical polishing (CMP) or an etch-back.
In FIG. 1t, the photoresist 20 is deposited on the substrate, and the photoresist 20 is partially removed to expose the interlayer insulation layer 38 provided over the S/D of the cell region X. Further, parts of the interlayer insulation layer 38 are removed to expose the gate insulation layer 24 above the S/D by using the photoresist 20 as an etch mask, and then the photoresist 20 is removed.
With reference to FIG. 1u, an N-type impurity of a high dose is ion-implanted by using the interlayer insulation layer 38, the upper insulation layer 30 and the spacer 34 as an ion implantation mask to form the second impurity region 36 of high density in the S/D of the cell region X, and then the photoresist 20 is removed. After the ion-implantation process, the annealing process of high temperature, e.g. about 800° C. is performed.
In FIG. 1v, the gate insulation layer 24 is removed (not shown) from the S/D of the cell region X, and a pad polysilicon layer 40 is formed by using polysilicon containing a conductive impurity on the semiconductor substrate 10. The pad polysilicon layer 40 is flattened through CMP or etch back so as to partially expose the spacer and the upper insulation layer 30. Then, the annealing process of a high temperature is performed, thus reducing possible defects on the surface of the semiconductor substrate 10 comprising the S/D below the pad polysilicon layer 40.
Though not shown in the drawing, an interlayer insulation layer is formed on the pad polysilicon layer 40. Further, the interlayer insulation layer above the source region is removed to form a first contact hole, and a bit line contact is formed to be electrically connected to the pad polysilicon layer 40 through the first contact hole. Then, another interlayer insulation layer is formed on the substrate, and both interlayer insulation layers above the drain region are removed, thus forming a second contact hole. Thereon, a storage electrode electrically connected to the pad polysilicon layer 40 of a cell transistor through the second contact hole, a dielectric layer and a plate electrode are formed sequentially, thereby completing a capacitor of a memory cell.
However, there are problems in the method of fabricating the transistor of semiconductor device according to the prior art. When ion-implanting the P-type impurity into the gate electrode of the PMOS transistor region, the P-type impurity penetrates the gate insulation layer during a subsequent annealing process and diffuses into the channel. This results in a drop in device performance.
Furthermore, ion-implanting impurities into the gate electrode must be performed several times. Thus, the ion-implantation process is complicated, lowering productivity. Embodiments of the invention address these and other limitations in the prior art.